What is a chip-on-wafer (CoW) package?

A Chip-on-Wafer-on-Substrate (CoWoS) package is a two-and-a-half-dimensional (2.5D) integrated circuit (IC) packaging technology developed by TSMC (Taiwan Semiconductor Manufacturing Company) for high-performance applications. Let%27s delve into the details:

1. Overview:
- CoWoS incorporates multiple dies side-by-side on a silicon interposer to achieve better interconnect density and performance.
- Individual chips are bonded through micro-bumps on the silicon interposer, forming a chip-on-wafer (CoW) configuration.
- The CoW is then thinned, exposing the through-silicon via (TSV) perforations.
- Following this, C4 bumps are formed, and the CoW is singulated.
- Finally, the CoWoS package is completed by bonding it to a package substrate.

2. Versions:
- TSMC has introduced several versions of CoWoS since its inception in 2012:
- CoWoS-1: The first generation, primarily used for large field-programmable gate arrays (FPGAs), had an interposer die area of up to ~800 mm².
- CoWoS-2: The second generation increased the interposer size considerably through mask stitching, with an interposer size of up to 1,700 mm² (referred to as CoWoS-XL2).
- The table below shows the evolution of CoWoS versions:

| Year | Size (x reticle) | Options | Bandwidth |
|----------|-----------------------|--------------------|---------------|
| 2012 | 1.25x (~1070 mm²) | Logic+Logic | - |
| 2016 | 1.5x (~1280 mm²) | Logic+Logic/HBM2 | 720 GB/s |
| 2017 | 1.75 (~1500 mm²) | Logic+Logic/HBM2 | 900 GB/s |
| 2019 | 1.85 (~1590 mm²) | Logic+Logic/HBM2 | 1 TB/s |
| 2020 | 2x (~1700 mm²) | Logic+Logic/HBM2E/3| 2.7 TB/s |
| ? | 3x (~2500 mm²) | - | - |

3. Additional Features:
- HK-MiM (High-K Metal-Insulator-Metal): Inserted between Metal1 and Metal2 layers of the Si interposer, it serves for system-level decoupling applications.
- Integrated Capacitor (iCAP): CoWoS deep trench capacitors with a standard cell size of 40 µm by 40 µm, achieving up to 340 nF/mm² capacitance density.

CoWoS not only reduces chip space but also minimizes power consumption and costs. It%27s a fascinating technology that bridges the gap between 2D and 3D IC packaging!

For more in-depth information, you can explore the [TSMC CoWoS WikiChip page](https://en.wikichip.org/wiki/tsmc/cowos).¹²

(1) Chip-on-Wafer-on-Substrate (CoWoS) - TSMC - WikiChip. https://en.wikichip.org/wiki/tsmc/cowos.
(2) Chip-on-Chip (CoC) Packaging - Amkor Technology. https://amkor.com/technology/chip-on-chip/.

icDirectory Limited | https://www.icdirectory.com/a/blog/what-is-a-chip-on-wafer-cow-package.html