How does the Miller capacitance affect MOSFET performance?
Technical Blog / Author: icDirectory / Date: Apr 06, 2024 15:04
Let%27s explore the impact of Miller capacitance on MOSFET performance in detail.

1. What is Miller Capacitance?:
- The Miller capacitance, also known as the reverse transfer capacitance (Cgd), is a parasitic capacitance inherent in MOSFETs.
- It arises due to the overlap between the gate and drain regions.
- When the gate voltage changes, it causes a voltage variation across Cgd.

2. Effects of Miller Capacitance:
- Switching Speed Reduction:
- During MOSFET switching transitions, Cgd couples the drain voltage variations back to the gate.
- This feedback effect slows down the switching speed.
- Miller Plateau:
- The Miller effect creates a plateau in the gate voltage during switching.
- This plateau delays the turn-on and turn-off times, affecting overall performance.
- Increased Electromagnetic Interference (EMI):
- Rapid voltage changes across Cgd generate high-frequency current spikes.
- These spikes contribute to EMI, affecting nearby circuits.

3. Design Considerations:
- Engineers must account for Miller capacitance during circuit design.
- Proper layout techniques can minimize its impact.
- Gate driver design and gate resistance play a role in mitigating Miller effects.

4. Applications:
- In power electronics, understanding Miller capacitance is crucial for optimizing switching behavior.
- High-frequency applications require careful consideration of this parasitic capacitance.

In summary, managing Miller capacitance is essential for achieving efficient and reliable MOSFET performance.

For more detailed information, you can refer to [this source](https://www.x-mol.com/paper/1430286197100101632) ².


(1) Miller Capacitance Cancellation to Improve SiC MOSFET%27s Performance in .... https://www.x-mol.com/paper/1430286197100101632.
(2) Power MOSFET Basics: Understanding Gate Charge and Using it to Assess .... https://www.vishay.com/docs/73217/an608a.pdf.
(3) Scopus - Miller Capacitance Cancellation to Improve SiC MOSFET%27s ... - NAE. https://www.nae.fr/scopus-miller-capacitance-cancellation-to-improve-sic-mosfets-performance-in-a-phase-leg-configuration/.
(4) Gate Capacitance and Miller Capacitance on the MOSFET. https://electronics.stackexchange.com/questions/83712/gate-capacitance-and-miller-capacitance-on-the-mosfet.

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