What is the Miller capacitance in a MOSFET?
Technical Blog / Author: icDirectory / Date: Apr 06, 2024 15:04
Let%27s delve into the concept of Miller capacitance in a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).

1. Definition:
- The Miller capacitance (often denoted as CGD or CGS) is an inherent parasitic capacitance in MOSFETs.
- It arises due to the overlap between the gate-drain or gate-source capacitances.
- Miller capacitance affects the high-frequency behavior of MOSFETs.

2. How It Occurs:
- When the gate voltage changes, the charge stored in the gate-drain or gate-source capacitance also changes.
- This varying charge causes an effective capacitance between the drain and gate (or source and gate).

3. Impact on Amplifiers:
- In amplifier circuits, the Miller capacitance can cause negative feedback.
- It reduces the effective gain and bandwidth of the amplifier.
- The Miller effect can be problematic in high-frequency applications.

4. Miller Plateau:
- The Miller capacitance creates a plateau in the voltage gain response.
- During switching, the MOSFET briefly enters this plateau, causing a delay in switching behavior.

5. Applications and Considerations:
- Engineers must account for Miller capacitance in high-frequency designs.
- Techniques like cascode configurations and bootstrapping help mitigate its effects.

In summary, understanding the Miller capacitance is crucial for designing efficient and stable MOSFET-based circuits, especially in high-frequency applications¹²³⁴⁵.


(1) voltage - Miller Capacitance in MOSFET - Electrical Engineering Stack .... https://electronics.stackexchange.com/questions/525167/miller-capacitance-in-mosfet.
(2) MOSFET Caps and Miller%27s Theorem - eecg.toronto.edu. https://www.eecg.toronto.edu/~johns/ece331/lecture_notes/13_mosCapsAndMiller.pdf.
(3) ECE 255, Miller E ect, Etc. - Purdue University College of Engineering. https://engineering.purdue.edu/wcchew/ece255s18/ece 255 s18 latex pdf files/ece255Lecture_26_April26_Miller_Effect_Etc.pdf.
(4) Power MOSFET Basics: Understanding Gate Charge and Using it to Assess .... https://www.vishay.com/docs/73217/an608a.pdf.
(5) Gate Capacitance and Miller Capacitance on the MOSFET. https://electronics.stackexchange.com/questions/83712/gate-capacitance-and-miller-capacitance-on-the-mosfet.

icDirectory Limited | https://www.icdirectory.com/b/blog/what-is-the-miller-capacitance-in-a-mosfet.html
  • What is the on-resistance of a MOSFET?
  • What is the pinch-off voltage in a MOSFET?
  • What is the drain current equation for a MOSFET in saturation?
  • What is the body effect in a MOSFET?
  • What is the difference between enhancement-mode and depletion-mode MOSFETs?
  • What are the different modes of operation for a MOSFET?
  • What is the purpose of the gate in a MOSFET?
  • What is the threshold voltage of a MOSFET?
  • What is the difference between N-channel and P-channel MOSFETs?
  • What are the three terminals of a MOSFET?
  • What does MOSFET stand for?
  • Discuss the impact of process technology on MCU soft error rate.
  • What are the challenges of implementing hardware security modules (HSMs) in MCUs?
  • Explain the concept of memory-mapped peripheral buses in MCUs.
  • What is the significance of the interrupt nesting level in MCUs?
  • How do MCUs handle power gating for peripheral modules?
  • What is the role of the memory protection region (MPR) in an MCU?
  • Discuss the impact of process scaling on MCU reliability.
  • What are the challenges of implementing secure firmware updates in MCUs?
  • Explain the concept of memory-mapped control registers in MCUs.