Let%27s explore the Nested Vectored Interrupt Controller (NVIC) in ARM-based microcontrollers (MCUs).

1. Overview:
- The NVIC is an integral part of ARM Cortex-M processors, closely linked to the CPU core logic.
- Its primary role is to manage and prioritize interrupts from various sources, both internal (peripherals) and external (pins).
- By efficiently handling interrupts, the NVIC ensures timely execution of critical tasks.

2. Key Functions:
- Interrupt Prioritization:
- The NVIC assigns priorities to different interrupt sources.
- Each interrupt can have one of four programmable priority levels.
- If multiple pending interrupts share the same priority, the NVIC gives precedence to the one with the lowest exception number (lowest interrupt vector address).
- Interrupt Enable/Disable:
- Individual interrupts can be enabled or disabled.
- When an interrupt condition occurs, the corresponding interrupt flag is set.
- The NVIC activates the interrupt only if it is enabled.
- Interrupt Handling:
- When an interrupt request is generated (e.g., by a peripheral), the NVIC sets the corresponding interrupt pending bit.
- To process the interrupt, it must be enabled in the NVIC.
- Interrupt Priority Registers:
- The NVIC maintains priority registers (IPR0 - IPR7) for each interrupt.
- Developers can configure the priority level for specific interrupts.
- External Interrupt Pins:
- All I/O pins are initially configured as general-purpose I/O (GPIO).
- Alternatively, they can be configured as external interrupt pins (EXTINT [15:0] & NMI).
- The External Interrupt Controller (EIC) allows fine-tuning of interrupt behavior (edge-sensitive, level-sensitive, etc.).
- Asynchronous Wake-Up:
- External pins can be configured as asynchronous to wake up the MCU from sleep modes.
- Even when all clocks are disabled, asynchronous pins can trigger wake-up events.
- Non-Maskable Interrupt (NMI):
- The NMI pin provides a special type of interrupt that doesn%27t require the EIC.
- It can be disabled by adjusting the NMISENSE bits in the NMICTRL register.

3. Use Cases:
- Safety-Critical Systems: NVIC ensures timely handling of safety-related interrupts (e.g., fault detection, emergency shutdown).
- IoT Devices: Efficient interrupt management is crucial for low-power IoT applications.
- Industrial Control: Precise handling of sensor data and communication interrupts.

In summary, the NVIC plays a pivotal role in orchestrating interrupts, maintaining system responsiveness, and ensuring reliable operation in ARM-based MCUs.

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References:
1. [Arm® Cortex®-M0+ Nested Vector Interrupt Controller](https://developerhelp.microchip.com/xwiki/bin/view/products/mcu-mpu/32bit-mcu/sam/arm-cortex-m0/nvic/)
2. [Chapter 8: The NVIC and Interrupt Control | GlobalSpec](https://www.globalspec.com/reference/23420/203279/Chapter-8-The-NVIC-and-Interrupt-Control)
3. [NVIC (Nested Vectored Interrupt Controller) | Toshiba Electronic ...](https://toshiba.semicon-storage.com/ap-en/semiconductor/knowledge/e-learning/tx03-series-microcontrollers/chapter2/nested-vectored-interrupt-controller.html) ¹²³


(1) Arm® Cortex®-M0+ Nested Vector Interrupt Controller. https://developerhelp.microchip.com/xwiki/bin/view/products/mcu-mpu/32bit-mcu/sam/arm-cortex-m0/nvic/.
(2) Chapter 8: The NVIC and Interrupt Control | GlobalSpec. https://www.globalspec.com/reference/23420/203279/Chapter-8-The-NVIC-and-Interrupt-Control.
(3) NVIC (Nested Vectored Interrupt Controller) | Toshiba Electronic .... https://toshiba.semicon-storage.com/ap-en/semiconductor/knowledge/e-learning/tx03-series-microcontrollers/chapter2/nested-vectored-interrupt-controller.html.

icDirectory Limited | https://www.icdirectory.com/b/blog/what-is-the-role-of-the-nvic-nested-vectored-interrupt-controller-in-arm-based-mcus.html